One of conventional apparatus for controlling a signal processing system to operate in high and low speed modes comprises a circuit for producing system clock signals and a control unit for controlling the signal processing system to operate in a predetermined mode. The circuit for producing system clock signals is controlled to produce system clock signals of a high or low speed in accordance with a high or low speed operation mode by the control unit. Therefore, the signal processing system can be switched over to operate in a low speed operation mode in accordance with system clock signals of a low speed in a case where a peripheral circuit of a low speed operation is included in the signal processing system.
According to the conventional apparatus for controlling a signal processing system to operate in high and low speed modes, however, there is a disadvantage that signals which are processed in accordance with high and low speed clock signals compete with each other on a bus in a case where a charge-over command by which the low speed operation mode is changed over to the high speed operation mode is produced in accordance with an error or a misinterpretation of a program when the low speed operation mode is being conducted. A further disadvantage is that a complicated interface circuit is required to be provided in a case where a peripheral circuit of a low speed operation is controlled to operate. A still further disadvantage is that an apparatus for controlling a signal processing system to operate in a low speed mode can not control a system of a high speed operation mode such as a system for the so-called television game.